Month: July 2021

In our other videos, we have shown how you can create a digital circuit and download to an FPGA board by using TINA’s Schematic Editor: (Programming FPGA boards with TINA using Schematic Design Entry)

and the VHDL hardware description language: (Programming FPGA boards in VHDL with TINA).

Now, in this video tutorial, our circuit, a full adder, will be based on the Verilog hardware description language.

The textual description of the hardware greatly enhances portability and reusability. By using hardware description languages describing the fundamental operations, structures and connections, virtually any logical circuit can be defined.

As we stated earlier, TINA works with schematics, but we can also place HDL macros, including VHDL and Verilog, in the design.

First we will test our circuit with Verilog circuit simulation in TINA.

The circuit operates like a half adder while Carry_In value is low.

• When both inputs are low while Carry_In is also low, then Sum and Carry_Out are also low.
• When just one input is low while Carry_In is low, then Sum is high and Carry_Out is also low.
• When both inputs are high when Carry_In is low, then Sum is low and Carry_Out is high.

Now, let’s see what happens when Carry_In is high.

• When Carry_In is high while both inputs are low, then Sum is high too and Carry_Out is low.
• When Carry_In is high while only one input is high, then Sum is low and Carry_Out is also high.
• When Carry_In is high while both inputs are high, then Sum and Carry_Out are also high.

If Carry_in is high, then the output values change as if we had added one to the full adder.

Next we will export the Verilog to the Xilinx Vivado software, compile it and load the resulting bitstream into the Basys 3 FPGA development board.

Finally we will present how our simulated full adder circuit works along with the programmed Basys 3 hardware and show  that in all cases, the results are exactly the same.

Check our other video “Programming FPGA Boards in VHDL with TINA”, where we use a Verilog component in FPGA design.

To learn more please click  here.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com

In our other videos, we have shown how you can create a digital circuit and download to an FPGA board by using TINA’s Schematic Editor. (Programming FPGA boards with TINA using Schematic Design Entry) and the Verilog hardware description language (Programming FPGA boards in Verilog with TINA).

Now, in this video tutorial  our circuit, a full adder, will be based on the VHDL  hardware description language.

As we stated earlier, TINA works with schematics, but we can also place HDL macros, including VHDL and Verilog, in the design.  

Now, let’s see an example, a full adder using the half-adder VHDL macros.

 Start TINA, then open the Full_Adder_VHDL.tsc from the TINA Examples folder.

Most digital circuits that perform addition or subtraction use full adder. This combinational circuit adds two binary digits and a carry-in to produce a sum and carry-out. This one-bit full-adder cell has three inputs (A, B, Carry_In) and two outputs (Sum, Carry_Out) by applying a half adder to accept the carry-in (Carry_In) input from the previous less-significant stage of a multiple bit adder. 

The circuit operates like a half adder while the Carry-In value is low. 

Start the simulation by pressing the Dig Interactive button. 

• When both inputs are low while Carry_In is also low, then Sum and Carry_Out are also low. 
• When just one input is low while Carry_In is low, then Sum is high and Carry_Out is also low. 
• When both inputs are high when Carry_In is low, then Sum is low and Carry_Out is high.

Now, let’s see what happens when Carry_In is high.

• When Carry_In is High while both inputs are low, then Sum is high too and Carry_Out is low. 
• When Carry_In is High while only one input is high then Sum is low and Carry_Out is also high. 
• When Carry_In is High while both inputs are high then Sum and Carry_Out are also high. 

If Carry_In is high, then the output values change as if we have added one to the full adder. 

In the following we will test our circuit in a real environment using the Digilent Basys 3 Artix-7 FPGA Trainer Board. 

As it can be seen, this circuit is already prepared for the FPGA Tool export. 

(See our previous video: Programming FPGA boards with TINA using Schematic Design Entry) 

In the following we will show how to  generate the source file for Xilinx Vivado 

Finally we will present how our simulated full adder circuit works along with the programmed Basys 3 hardware.

As you can see, in all cases, the results are exactly the same.

This is a great example of demonstrating the power of simulation, since you can test and debug circuits even before realizing them, and in our case before downloading to FPGA, where if there were any issues, it would be extremely hard to find the problem.

Check our other video “Programming FPGA Boards in Verilog with TINA”, where we use a Verilog component in FPGA design.

To learn more please click  here.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com

In this tutorial video we will show how to create a digital circuit and download it to a Digilent Basys 3 FPGA board by using TINA’s Schematic Editor.

In a similar way it is also possible to download digital circuits to the FPGA of DesignSoft’s LabXplorer.

The schematic design may contain gates or other built-in digital components in TINA. Also it may contain macros defining digital components with hardware description languages such as VHDL or Verilog.

In this video, we use a free Xilinx tool, Vivado, which is required for the FPGA in Digilent Basys 3.

As demonstration we use a half adder circuit which you can find in the Example folder of TINA.

Getting ready to test the circuit in real FPGA development board environment

Before testing our circuit in a real FPGA development board environment, we need to extend our schematic with FPGA Pin connectors. We add 2 Pin connectors to the inputs and 2 Pins to the outputs.

Next, we rename the FPGA input and output Pins (including their labels) accordingly as those on the FPGA boards.

Next, we present how to generate the source file for Xilinx Vivado.

Note that TINA always creates  vhd file from any type of
representation of the digital circuit. That is, schematic diagrams, VHDL, Verilog codes or their mix are always translated into a vhd file for Vivado.

The xdc – Xilinx Design Constraints – guides the Xilinx software on which physical pins on the FPGA will be the inputs and outputs. The xdc is made from the FPGA pin settings we made previously.

Creating the Vivado project and programming the hardware

Next, we need to create the Vivado project to produce downloadable content.

As soon as we finish programming the hardware we can start testing our simulated Half Adder circuit and see how it works along with the programmed Basys 3 hardware.

We will change the virtual switches in TINA by clicking them on the screen, and at the same time we will also change the real switches on the Basys 3 board.

• If both inputs are low, then Sum and Carry are also low. 
• If just one input is high, then Sum is high and Carry is low.
• If both inputs are high, then Sum is low and Carry is high.

As you can see, in all cases the results are exactly the same.

This is a great example of demonstrating the power of simulation since you can test and debug circuits even before realizing them, and in our case before downloading to FPGA, where if there were any issues it would be extremely hard to find the problem.

To watch our tutorial and learn more please click  here.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com

In our other videos, we have shown how you can create a digital circuit and download to an FPGA board by using TINACloud’s Schematic Editor: (Programming FPGA boards with TINACloud using Schematic Design Entry)

and the VHDL hardware description language: (Programming FPGA boards in VHDL with TINACloud).

Now, in this video tutorial, our circuit, a full adder, will be based on the Verilog hardware description language.

The textual description of the hardware greatly enhances portability and reusability. By using hardware description languages describing the fundamental operations, structures and connections, virtually any logical circuit can be defined.

As we stated earlier, TINACloud works with schematics, but we can also place HDL macros, including VHDL and Verilog, in the design.

First we will test our circuit with Verilog circuit simulation in TINACloud.

The circuit operates like a half adder while Carry_In value is low.

• When both inputs are low while Carry_In is also low, then Sum and Carry_Out are also low.

• When just one input is low while Carry_In is low, then Sum is high and Carry_Out is also low.

• When both inputs are high when Carry_In is low, then Sum is low and Carry_Out is high.

Now, let’s see what happens when Carry_In is high.

• When Carry_In is high while both inputs are low, then Sum is high too and Carry_Out is low.

• When Carry_In is high while only one input is high, then Sum is low and Carry_Out is also high.

• When Carry_In is high while both inputs are high, then Sum and Carry_Out are also high.

If Carry_in is high, then the output values change as if we had added one to the full adder.

Next we will export the Verilog to the Xilinx Vivado software, compile it and load the resulting bitstream into the Basys 3 FPGA development board.

Finally we will present how our simulated full adder circuit works along with the programmed Basys 3 hardware and show  that in all cases, the results are exactly the same.

Check our other video “Programming FPGA Boards in VHDL with TINACloud”, where we use a Verilog component in FPGA design.

To learn more please click  here.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com