Author: Michael Koltai

Creating Analog Components with Verilog-AMS

Hardware Description Languages (HDL) are powerful tools to describe and simulate complex electronic devices.

In this tutorial video

we will show how you can create a macro from a Verilog-AMS (.vams) code and use in TINA. You can create macros from VHDL, Verilog and Verilog-A files in a similar way.

Watch our tutorial video to see how  you can create a macro from a Verilog-AMS (.vams) code and use in TINA.

Download the FREE trial demo of TINA Design Suite and get:

1. One year free access to TINACloud (the cloud-based, multi-language, installation-free online version of TINA now running in your browser anywhere in the world.)
2. An immediate 20% discount from the offline version of TINA
3. Free license for your second computer, laptop etc.

Creating Analog Components with Verilog-A

Hardware Description Languages (HDL) are powerful tools to describe and simulate complex electronic devices.

In this tutorial video

we will show how you can create a macro from a Verilog-A (.va) code and use in TINA. You can create macros from VHDL, Verilog and Verilog-AMS files in a similar way.

Watch our tutorial video to see how  you can create a macro from a Verilog-A (.va) code and use in TINA.

Download the FREE trial demo of TINA Design Suite and get:

1. One year free access to TINACloud (the cloud-based, multi-language, installation-free online version of TINA now running in your browser anywhere in the world.)
2. An immediate 20% discount from the offline version of TINA
3. Free license for your second computer, laptop etc.

www.tina.com

Hardware Description Languages are powerful tools to describe and simulate complex electronic devices.

In this tutorial video we will show how you can create a macro from a Verilog-A (.va) code and use in TINA.

You can create macros from VHDL, Verilog and Verilog-AMS files in a similar way.

You can create a macro from any .vhd / .v / .va / .vams file that contains an entity (interface to the outside world) with its architecture (description of the hardware).

Files with .vhd extension are VHDL files, with .v extension are Verilog files, with .va extension are Verilog-A files and with .vams extension are Verilog-AMS files.

The ports declared in the interface part will automatically appear in the macro symbol (shape). You can associate an automatic rectangular block or a schematic symbol from TINA’s library with the macro.

In case of automatic rectangular blocks you can edit and reposition the interface pins.

Let’s demonstrate the details.

Open TINA

Click the Tools menu

Select New Macro Wizard…

Type a name for the new macro In our case: JFET1

Change the Settings from Current circuit to From file

Click the Open icon

Select TINA examples

Open the Examples and then the Verilog-A folder

Change the file type to .va

Open the Device Models folder then Select the jfet.va file and

Click Open

Press the Next button

You can either Select the Auto generate shape or you can load a shape from the library

Let’s Select first the Auto Generate shape option

then Click Next

Check the interface line

Change the orientation of “d” into up, and “s” into down

You can also browse the Verilog-A code

Click Next

and save the macro (jfet1.tsm) into the default Macrolib folder.

You can insert the Macro by pressing the Insert button or you can select the “Insert/Macro…” from the menu.

Click the Insert button

The macro will be attached to your cursor. Place it wherever you wish on the workspace.

Let’s demonstrate the case when you select the “Load shape from the library” option.

Click the  Tools menu

Select New Macro Wizard

and let’s name the new macro as JFET2.

After selecting the jfet.tsm file, press the Next button

Select the TINAICS folder

Find the JFET symbol by clicking the long vertical button and then using the scrollbar

Click Next

Check if the uppercase D, G, S symbol pins are properly connected with the lowercase d, g, s macro parameters

if not, you can easily update the connections by dragging the connection labels

In our case no changes are needed.

Click Next

then the Insert button

Place the Macro on the workspace

By double-clicking the macro, then pressing the Enter Macro button you can check its content

The content of the macro appears

Now close the HDL Editor window of TINA

Let’s create the following circuit to test the new transistor model:

Select the Voltage Source and the Voltage Generator from the Sources Toolbar

Next, select the Current Arrow from the Meters Toolbar, then  rotate it

Click the Insert menu

Select Macro

Select User Macros

Select the jfet2.tsm, then click Open

The Verilog-A macro will be attached to your cursor, you can place it on the workspace

Draw the wires to connect the components

Double-click the labels to rename them

and you can also replace the labels if necessary by dragging it while it is selected

Let’s test the circuit by Running Analysis

DC Analysis

Click Analysis on the Toolbar

Select DC Analysis

and then DC Transfer Characteristic…

The DC Transfer Characteristic dialog box appears.

Check if the parameters under the Main sweep tab are as shown on the screen

Note that TINA also allows Nested Sweep in the  DC Transfer Characteristic analysis which makes the calculation of device characteristics easier

Click the nested sweep tab and check the parameters shown on the screen.

According to these parameters

9  ID versus VG curves will be calculated with 9 different VG values including

VG= – 2 and VG = 0 as well.

Click OK to run the DC Analysis

Our test circuit works as expected.

Creating Macros from Verilog

Hardware Description Languages (HDL) are powerful tools to describe and simulate complex electronic devices.

In this tutorial video

we will show how you can create a macro from a Verilog (.v) code and use       in TINA. You can create macros from VHDL, Verilog-A and Verilog-AMS files in a similar way.

Watch our tutorial video to see how  you can create a macro from a Verilog (.v) code and use  in TINA.

Download the FREE trial demo of TINA Design Suite and get:

1. One year free access to TINACloud (the cloud-based, multi-language, installation-free online version of TINA now running in your browser anywhere in the world.)
2. An immediate 20% discount from the offline version of TINA
3. Free license for your second computer, laptop etc.

You can also find below the script of the video: 

Using Hardware Description Languages in TINA, Part 2: Creating Macros from Verilog

In this tutorial video we will show how you can create a macro from a Verilog (.v) code and use in TINA. You can create macros from VHDL, Verilog-A and Verilog-AMS files in a similar way.

For example consider the following Verilog interface:

module half_add (A, B, S, C);   

input A, B;

output S, C;

In this case the A,B ports will appear on the left side and the S,C ports will appear on the right side of the macro shape.

Let’s see how to make a macro from the following Verilog code (a half adder):

module half_add(A, B, S, C);  

input A, B;

output S, C;

assign S = A ^ B;

assign C = A & B;

endmodule

Note that this Verilog code is much simpler than the equivalent VHDL code. This is one of the great advantages of Verilog.

The essential Verilog code of the half adder is 2 lines long only.

Let’s demonstrate the details.

Open TINA

Click the Tools menu

Select New Macro Wizard

Type a name for the new macro In our case: Half adder Verilog

Change the Settings from Current circuit to From file

Click the Open icon

Change the file type to .v

Select TINA examples

Select Examples

Click the Verilog folder

Click Open

Select the Half adder Verilog.v file and press Open

Press the Next button to save the macro,

and save the macro into the default Macrolib folder.

Now you can insert the Macro by pressing the Insert button or you can select the “Insert/Macro…” from the menu.

Click the Insert button

The macro will be attached to your cursor. Place it wherever you wish on the workspace.

To see the content of the macro double-click on it and press the Enter Macro button

The content of the macro appears.

Close the TINA HDL Editor window

Let’s test our newly created macro in TINA’s Digital interactive mode along with the previously created VHDL macro

(See Using Hardware Description languages in TINA, part 1)

Let’s open our previously created Half_ Adder VHDL macro.TSC circuit.

Here is the circuit with two High-Low digital switches, one for each of the A,B inputs, and two logic indicators. We will copy the circuit, then we will change the macro into the Half adder Verilog macro

To select the circuit click at the corner of the area to be selected, hold down the left mouse button then move the mouse and release the left mouse button at the opposite corner.

Click the Copy then the Paste button on the toolbar. Your circuit will be attached to your cursor.  Position it by moving the mouse to the required position and press the left mouse button.

Deselect the circuit by clicking an empty spot.

Click the Half adder VHDL macro to be selected then delete it by pressing the Del key on the keyboard.

Click the Insert menu

Select Macro

Select User Macros

Select the Half adder Verilog.TSM, then click Open

The Verilog macro will be attached to your cursor, you can move and insert it into the place of the deleted VHDL macro.

Let’s test the 2 circuits

Select the Digital interactive mode with the narrow “Select Interactive mode” button on the Toolbar

Press the Dig  button

The logic levels of the nodes appear, Red for High. Blue for Low.

The logic indicators will also show the logic level of the outputs in a Red square for High, and empty square for Low.

Both Half_adder circuits work as required.

Creating Macros from a VHDL code

Hardware Description Languages (HDL) are powerful tools to describe and simulate complex electronic devices.

In this tutorial video

we will show how you can create a macro from a VHDL (.vhd) code and use     in TINA. You can create macros from Verilog, Verilog-A and Verilog-AMS files in a similar way.

Watch our tutorial video to see how  you can create a macro from a VHDL (.vhd) code and use         in TINA.

Download the FREE trial demo of TINA Design Suite and get:

1. One year free access to TINACloud (the cloud-based, multi-language, installation-free online version of TINA now running in your browser anywhere in the world.)
2. An immediate 20% discount from the offline version of TINA
3. Free license for your second computer, laptop etc.

www.tina.com

You can also find below the script of the video:

Using Hardware Description Languages in TINA, Part 1: Creating Macros from a VHDL code

Hardware Description Languages are powerful tools to describe and simulate complex electronic devices. In this tutorial video we will show how you can create a macro from a VHDL code and use in TINA. You can create macros from Verilog, Verilog-A and Verilog-AMS files in a similar way.

You can create a macro from any .vhd , .v , .va, .vams file that contains an entity (interface to the outside world) with its architecture (description of the hardware).

The meaning of the file extensions is as follows:

Files with .vhd extension are VHDL files,

with .v extension are Verilog files,

With .va extension are Verilog-A files and

with .vams extension are Verilog-AMS files.

The ports declared in the interface part will automatically appear in the macro symbol (shape). By default, the input ports of the interface will appear on the left side of the generated macro shape and the output ports of the interface will appear on the right side, but by editing the generated macro you can change this arrangement.

For example consider the following VHDL interface:

ENTITY e_Half_add_entity IS PORT(

A : IN std_logic;

S : OUT std_logic;

C : OUT std_logic;

B : IN std_logic );

END e_Half_add_entity;

In this case the A,B ports will appear on the left side

and the S,C ports will appear on the right side of the macro shape.

Now let’s see how to make a macro from the following VHDL code (a half adder):

LIBRARY ieee, tina;

use ieee.std_logic_1164.all;

use std.textio.all;

USE tina.primitives.all;

————————————

— entity section

————————————

ENTITY e_Half_add_entity IS PORT(

A : IN std_logic;

S : OUT std_logic;

C : OUT std_logic;

B : IN std_logic );

END e_Half_add_entity;

————————————

— architecture section

————————————

ARCHITECTURE a_Half_add_arch of e_Half_add_entity IS

constant delay : time := 20 ns;

BEGIN

S< = (A xor B) after delay;

C< = (A and B) after delay;

END a_Half_add_arch;

Note that the essential code of the half adder is 2 lines long only

Open TINA

Click the Tools menu

Select New Macro Wizard

Type a name for the new macro

In our case: Half_adder_VHDL

Change the Settings from Current circuit to From file

Click the Open icon

Change the file type to VHDL

From the TINA program folder

Select Examples

Open the VHDL folder

Select the Half_adder_VHDL.vhd file and press Open

Press the Next button to save the macro and save the macro into the default Macrolib folder.

You can insert the Macro by pressing the Insert button or you can select the “Insert/Macro” from the menu.

Click the Insert button

To see the content of the macro double-click on it and press the Enter Macro button

The content of the macro appears

Let’s test our newly created macro in TINA’s Digital interactive mode.

To do this, place two High-Low digital switches from the Switches toolbar, one for each of the A,B inputs, and two logic indicators.

Now select the Digital interactive mode with the narrow “Select Interactive mode” button on the Toolbar

then press the  Dig   button

The logic levels of the nodes appears, Red for High. Blue for Low.

Click the switches to change the input states.

The logic indicators will also show the logic level of the outputs in a

Red square for High, and empty square for Low.

The Half adder circuit works as required.

In our example so far the terminals or pins of the macro were placed automatically.

You can change the automatic pin arrangement of an automatically generated macro by editing its header.

For example the header in the previous example is

————————————

— TINA HDL Macro Description Begin

—

— entity_name:e_half_add_entity;

— arch_name:ignored;

— ports:a,b;s,c;

— Mode:VHDLTyp;

—

— TINA HDL Macro Description End

———————————-

The pin arrangement is determined by the following line:

ports:A,B;S,C;

the ports before the first semicolon (;) are placed on the left while the rest are

placed on the right side of the macro box.

If you change the port line to Ports as follows:

A,B,S;C

A, B, S will be placed on the left side and C on the right side of the macro box.

You can also change the vertical order of the pins by changing the order of the pins in the list.

Let’s see how to convert the previous Macro:

Half_adder_VHDL into a new Macro called: Half_adder_VHDL_modified

Double-click the macro and press the Enter Macro button

Let’s change the ports line to as follows:

ports:A,B,S;C;

Select File

Select Save as

Save the modified code. We will save it under the name: Half_adder_VHDL_modified.vhd

Close the TINA HDL Editor

In the pop-up window the following message appears:

Macro has been modified. Confirm changes?

Click No

Let’s create a new macro with the modified pin arrangement

Click the Tools menu

Select New Macro Wizard Enter the name of the new macro:In our case: Half_adder_VHDL_modified

Change the Settings from Current circuit to From file

Click the  Open icon

Invoke the place where your newly created macro is saved. In our case the Downloads folder

Change the file type to VHDL

Select the Half_adder_VHDL_modified file, then click Open

Press the Next button to save the macro,

and save the .TSM file into the default Macrolib folder.

Click the Insert button

The modified macro with the revised pinout version will be attached to your cursor and you can place it anywhere on the workspace

By double-clicking the modified Macro, then pressing the Enter Macro button you can see the content of the macro with the revised pin arrangement