Author: Michael Koltai

In this tutorial video our circuits are counters. The counter is a widely used sequential logic, where the output depends on the sequence of past inputs and a present value of the input signals.

In the case of a counter, the input signal is the clock, and the output value represents a number.  

The counter circuit is usually built up with flip-flops. 

Now, let’s see our first example, a binary up counter. 

The counter is constructed from four, rising edge sensitive D flip-flops counting from 0 to 15. Flip-flops store the count until the next event, when the clock signal produces a low to high transition. 

The least significant bit is QA. The clock source is 1Hz for good interactivity. 

Following the practice, we assign a short clear pulse by PS at the very beginning before the counting sequence to reset the flip-flops. 

The full name of the circuit is “asynchronous binary up counter.” Asynchronous, because each flip-flop has a distinctive clock, usually from the previous stage. 

Now, press the Transient interactive button. 

Let’s examine the circuit operation. 

When the clock is changing low to high the indicator turns red, then the least significant flip-flop, U1, will toggle, and this effect propagates through each flip-flop. This ripple phenomenon causes a delay in the nanosecond domain, but if we don’t care about an immediate result, short transients are acceptable. 

Eextending our schematic with FPGA pin connectors

Now, before testing our circuit in a real FPGA environment, we need to extend our schematic with FPGA pin connectors as we have shown in our previous video. We will use a Digilent BASYS3 FPGA board. 

We shouldn’t forget what resources our FPGA board offers. Regarding the BASYS3 board, we should note that such a board has only one clock generator with 100MHz output frequency. 

Since the board doesn’t provide a 1Hz clock, we have to apply a prescaler which will produce that [PS1] from the BASYS3 100MHz oscillator.

Applying a Prescaler

Now, let’s insert this prescaler as a macro which has been written in VHDL. 

Select Insert Global Macro… from the Insert menu denoted by a green plus sign, then in the Global macros dialog select the prescaler and click OK.

Place the macro on the workspace, then pan the circuit by holding down the left mouse button while moving the mouse.

Now, you can attach the macro to the input of the circuit so that the clock frequency will be divided at the input of the counter.

The prescaler macro has one input named “Clk” and one output named “PClk”.

The clock frequency at Clk input is 100MHz, and it is 1Hz at the PClk output.  

The prescaler itself is also a counter. When the counter reaches 50,000,000 the PClk output is toggled so that the frequency of the clock at this output is 1Hz. 

This is an additional logic to reach slow, human readable operation speed.  Now, add the FPGA pin connectors to the circuit as shown next. The simulation of this circuit must be handled with care. Because the prescaler has to count to a very large number before the output toggles, we have to slow down this module.

Therefore, in the simulation, change the input clock frequency to 100Hz and change the macro code so that the counter counts up to 50 instead of 50,000,000.  This way we will have a 1Hz clock coming out of the prescaler for the simulator. 

Press the TR button to start the simulation.

A counter can count not only a series of pulses, but other events too. For example, the number of times a push button has been pressed .

Replacing the Clock source with a Push button

To demonstrate this, let’s go back to our original circuit.

Replace the clock source with a push button.

Let the push button (PB) generate a high level when it is pressed and a low level when it is at rest.

The low level needs a resistor. 

Thus, it will work the same way as the button does on the BASYS3 board.

Start Transient interactive analysis by pressing the TR button, then click the push button (PB) to step the counter. When the button is pressed, a rising edge occurs on the clock input of the first flip-flop, and the counter outputs will produce the next binary code. 

Placing a contact debouncing VHDL macro

Here, we note that the mechanical switches and push buttons have contact bouncing problems. If we press a button once in the real world, that may generate a series of pulses. That’s why we place a contact debouncing VHDL macro at the counter input. 

Before we do that, remove the push button and the resistor. These are not necessary because they are on the board and don’t belong to the synthesizable logic. 

Remove the pulse source, too.

The FPGA will take care of resetting the flip-flops. 

Now, let’s insert the macro named “debouncer”, which has two inputs (Clk and PB) and two outputs (PBDown and PBUp).

Clk is connected to the BASYS 3 clock port, and PB is connected to the center push button (btnC) of the board. Output PBDown is connected to the clock input of the first counter flip-flop.

Click the Insert menu, then select Insert Global Macro. Select the debouncer, then click OK.

Place a Clock from the Sources Toolbar. Change its frequency to 100M and rename its label as “Clock”, then connect it to the debouncer macro. The debouncer will eliminate the unwanted glitches by resampling the button’s signal with a low frequency and constructing a single pulse when the button is pressed or released. 

Place 4 more FPGA pin connectors and connect them to the Logic indicators (QA, QB, QC, QD).

Set their parameters and rename them as we did previously.

Here, every time the center push button is pressed, a pulse is sent to the counter and as a result it counts up by one.

To learn more please click  here.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com

In our other videos, we have shown how you can create a digital circuit and download to an FPGA board by using TINA’s Schematic Editor: (Programming FPGA boards with TINA using Schematic Design Entry)

and the VHDL hardware description language: (Programming FPGA boards in VHDL with TINA).

Now, in this video tutorial, our circuit, a full adder, will be based on the Verilog hardware description language.

The textual description of the hardware greatly enhances portability and reusability. By using hardware description languages describing the fundamental operations, structures and connections, virtually any logical circuit can be defined.

As we stated earlier, TINA works with schematics, but we can also place HDL macros, including VHDL and Verilog, in the design.

First we will test our circuit with Verilog circuit simulation in TINA.

The circuit operates like a half adder while Carry_In value is low.

• When both inputs are low while Carry_In is also low, then Sum and Carry_Out are also low.
• When just one input is low while Carry_In is low, then Sum is high and Carry_Out is also low.
• When both inputs are high when Carry_In is low, then Sum is low and Carry_Out is high.

Now, let’s see what happens when Carry_In is high.

• When Carry_In is high while both inputs are low, then Sum is high too and Carry_Out is low.
• When Carry_In is high while only one input is high, then Sum is low and Carry_Out is also high.
• When Carry_In is high while both inputs are high, then Sum and Carry_Out are also high.

If Carry_in is high, then the output values change as if we had added one to the full adder.

Next we will export the Verilog to the Xilinx Vivado software, compile it and load the resulting bitstream into the Basys 3 FPGA development board.

Finally we will present how our simulated full adder circuit works along with the programmed Basys 3 hardware and show  that in all cases, the results are exactly the same.

Check our other video “Programming FPGA Boards in VHDL with TINA”, where we use a Verilog component in FPGA design.

To learn more please click  here.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com

In our other videos, we have shown how you can create a digital circuit and download to an FPGA board by using TINA’s Schematic Editor. (Programming FPGA boards with TINA using Schematic Design Entry) and the Verilog hardware description language (Programming FPGA boards in Verilog with TINA).

Now, in this video tutorial  our circuit, a full adder, will be based on the VHDL  hardware description language.

As we stated earlier, TINA works with schematics, but we can also place HDL macros, including VHDL and Verilog, in the design.  

Now, let’s see an example, a full adder using the half-adder VHDL macros.

 Start TINA, then open the Full_Adder_VHDL.tsc from the TINA Examples folder.

Most digital circuits that perform addition or subtraction use full adder. This combinational circuit adds two binary digits and a carry-in to produce a sum and carry-out. This one-bit full-adder cell has three inputs (A, B, Carry_In) and two outputs (Sum, Carry_Out) by applying a half adder to accept the carry-in (Carry_In) input from the previous less-significant stage of a multiple bit adder. 

The circuit operates like a half adder while the Carry-In value is low. 

Start the simulation by pressing the Dig Interactive button. 

• When both inputs are low while Carry_In is also low, then Sum and Carry_Out are also low. 
• When just one input is low while Carry_In is low, then Sum is high and Carry_Out is also low. 
• When both inputs are high when Carry_In is low, then Sum is low and Carry_Out is high.

Now, let’s see what happens when Carry_In is high.

• When Carry_In is High while both inputs are low, then Sum is high too and Carry_Out is low. 
• When Carry_In is High while only one input is high then Sum is low and Carry_Out is also high. 
• When Carry_In is High while both inputs are high then Sum and Carry_Out are also high. 

If Carry_In is high, then the output values change as if we have added one to the full adder. 

In the following we will test our circuit in a real environment using the Digilent Basys 3 Artix-7 FPGA Trainer Board. 

As it can be seen, this circuit is already prepared for the FPGA Tool export. 

(See our previous video: Programming FPGA boards with TINA using Schematic Design Entry) 

In the following we will show how to  generate the source file for Xilinx Vivado 

Finally we will present how our simulated full adder circuit works along with the programmed Basys 3 hardware.

As you can see, in all cases, the results are exactly the same.

This is a great example of demonstrating the power of simulation, since you can test and debug circuits even before realizing them, and in our case before downloading to FPGA, where if there were any issues, it would be extremely hard to find the problem.

Check our other video “Programming FPGA Boards in Verilog with TINA”, where we use a Verilog component in FPGA design.

To learn more please click  here.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com

In this tutorial video we will show how to create a digital circuit and download it to a Digilent Basys 3 FPGA board by using TINA’s Schematic Editor.

In a similar way it is also possible to download digital circuits to the FPGA of DesignSoft’s LabXplorer.

The schematic design may contain gates or other built-in digital components in TINA. Also it may contain macros defining digital components with hardware description languages such as VHDL or Verilog.

In this video, we use a free Xilinx tool, Vivado, which is required for the FPGA in Digilent Basys 3.

As demonstration we use a half adder circuit which you can find in the Example folder of TINA.

Getting ready to test the circuit in real FPGA development board environment

Before testing our circuit in a real FPGA development board environment, we need to extend our schematic with FPGA Pin connectors. We add 2 Pin connectors to the inputs and 2 Pins to the outputs.

Next, we rename the FPGA input and output Pins (including their labels) accordingly as those on the FPGA boards.

Next, we present how to generate the source file for Xilinx Vivado.

Note that TINA always creates  vhd file from any type of
representation of the digital circuit. That is, schematic diagrams, VHDL, Verilog codes or their mix are always translated into a vhd file for Vivado.

The xdc – Xilinx Design Constraints – guides the Xilinx software on which physical pins on the FPGA will be the inputs and outputs. The xdc is made from the FPGA pin settings we made previously.

Creating the Vivado project and programming the hardware

Next, we need to create the Vivado project to produce downloadable content.

As soon as we finish programming the hardware we can start testing our simulated Half Adder circuit and see how it works along with the programmed Basys 3 hardware.

We will change the virtual switches in TINA by clicking them on the screen, and at the same time we will also change the real switches on the Basys 3 board.

• If both inputs are low, then Sum and Carry are also low. 
• If just one input is high, then Sum is high and Carry is low.
• If both inputs are high, then Sum is low and Carry is high.

As you can see, in all cases the results are exactly the same.

This is a great example of demonstrating the power of simulation since you can test and debug circuits even before realizing them, and in our case before downloading to FPGA, where if there were any issues it would be extremely hard to find the problem.

To watch our tutorial and learn more please click  here.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com

In our other videos, we have shown how you can create a digital circuit and download to an FPGA board by using TINACloud’s Schematic Editor: (Programming FPGA boards with TINACloud using Schematic Design Entry)

and the VHDL hardware description language: (Programming FPGA boards in VHDL with TINACloud).

Now, in this video tutorial, our circuit, a full adder, will be based on the Verilog hardware description language.

The textual description of the hardware greatly enhances portability and reusability. By using hardware description languages describing the fundamental operations, structures and connections, virtually any logical circuit can be defined.

As we stated earlier, TINACloud works with schematics, but we can also place HDL macros, including VHDL and Verilog, in the design.

First we will test our circuit with Verilog circuit simulation in TINACloud.

The circuit operates like a half adder while Carry_In value is low.

• When both inputs are low while Carry_In is also low, then Sum and Carry_Out are also low.

• When just one input is low while Carry_In is low, then Sum is high and Carry_Out is also low.

• When both inputs are high when Carry_In is low, then Sum is low and Carry_Out is high.

Now, let’s see what happens when Carry_In is high.

• When Carry_In is high while both inputs are low, then Sum is high too and Carry_Out is low.

• When Carry_In is high while only one input is high, then Sum is low and Carry_Out is also high.

• When Carry_In is high while both inputs are high, then Sum and Carry_Out are also high.

If Carry_in is high, then the output values change as if we had added one to the full adder.

Next we will export the Verilog to the Xilinx Vivado software, compile it and load the resulting bitstream into the Basys 3 FPGA development board.

Finally we will present how our simulated full adder circuit works along with the programmed Basys 3 hardware and show  that in all cases, the results are exactly the same.

Check our other video “Programming FPGA Boards in VHDL with TINACloud”, where we use a Verilog component in FPGA design.

To learn more please click  here.

You can learn more about TINA here: www.tina.com

You can learn more about TINACloud here: www.tinacloud.com