In this video, first, we will demonstrate how to simulate and synthesize a circuit displaying prime numbers using a PIC MCU VHDL code.
In the end, we will download the circuit’s configuration file to the Digilent Basys 3 FPGA board.
In our circuit, PIC16F84_Prime_number_generator, the PIC MCU model is written in VHDL. The VHDL code is the functional model of a PIC16F84 8-bit microcontroller with initialized flash program memory.
Looking at the VHDL code in TINA HDL editor
First, we look at the VHDL code using TINA HDL Editor.
The top-level entity is rtl_pic.
In the architecture section bound to the rtl_pic entity (line 1828), we instantiate and connect the main components.
These components are the pic_core (line 1830), the 1k*14 bits flash_rom (line 1890), and the PIC16F_RAM file register (line 1898).
From line 1941, the instantiation statements connect these declared components to signals in the architecture (1941–2002), followed by auxiliary VHDL code to support reset and IO updates.
Looking at the C code in the MPLAB editor
Next, we will check the program code, written in C and converted to this VHDL code.
The project was created, and the program was developed with the free version of Microchip MPLAB IDE and their Microchip XC8 compiler.
Let’s open the MPLAB editor.
MPLAB editor
First, we define SIM, indicating that we are running a simulation (line 3).
If SIM is defined, then other constants are created in lines 6–10.
The XTAL FREQ is the processor frequency for the simulation.
The other parameters are for handling the display.
The code writes prime numbers between 1 and 9999 with the help of a for loop starting from line 98.
If a number is prime, we will generate the digits and display the number.
We have 8 bits to write a digit (PORTB) and 4 bits (PORTA) to select which one to display.
One digit is displayed for a very short time in the millisecond domain.
When a digit is displayed, the other digits are dark. This process is performed from line 107.
Circuit simulation
Prime number generator circuit. Circuit simulation
After that, we return to TINA’s Schematic Editor to run digital simulation. Then we go back to the MPLAB editor to make the main difference in the C code for the synthesis, like the processor speed (100 MHz). This is the oscillator frequency of the BASYS3 FPGA board. Next, we compile the project and convert the result – the executable binary – into VHDL.
MBLAB editor. Comment the SIM definition
The code is placed in the flash ROM component of our VHDL PIC model.
Testing our circuit in a real environment
Finally, we will test our circuit, ” PIC16F84_Prime_number_generator_BASYS3” in a real environment using the Digilent BASYS3 FPGA board.
As expected, we can see the prime numbers written on the display.
Testing the circuit in a real environment using the Digilent Basys 3 FPGA board
In this video our counter will be based on the VHDL hardware description language.
In our first example, Binary Counter VHDL circuit, we replace the flip flops by a macro which has been written in VHDL.
The macro has two inputs, one for the Clock (clk) and another for the active-low reset (resetn). Clk is connected to the Clock Source, and resetn is connected to the reset Pulse Source.
The four outputs (QA, QB, QC, QD) provide the counter value.
The Binary Counter entity has the same inputs and outputs as the macro shape.
simulation of the binary counter vhdl circuit
Binary Counter VHDL circuit
We can start the simulation by pressing the Transient Interactive button.
When the clock is changing low to high the indicator turns red then the QA, the least significant bit, toggles. Then, at each rising edge of the clock, the count value goes up by one.
When the Counter reaches the maximum value (binary 1111), the output goes zero.
testing our circuit with the Terasic de10-Lite FPGA board
Before testing our circuit in a real FPGA environment, we need to extend our schematic with FPGA pin connectors. Since the board doesn’t provide a one hertz Clock, we have to apply a Prescaler which will produce that from the DE10-Lite 50 MHz Oscillator.
The prescaler macro has one input named clk and one output named pclk. The clock frequency at clk input is 100 megahertz and it is one hertz at the pclk output by default. To adjust the VHDL code to the board 50 MHz frequency, we modify the ‘Presc < 50000000’ expression constant to 25 million in the Prescaler macro.
The prescaler itself is also a counter. When the counter reaches 25 million the PClk output is toggled, so that the frequency of the clock at this output is 1Hz.
Next, we will place the FPGA Pin connectors. We will attach the first Pin connector to the Clock input before the Prescaler . Then, we will connect 4 more FPGA pin connectors to the 4 outputs of the circuit and assign them to the LEDs: LEDR[0], LEDR[1], LEDR[2] and LEDR[3] .
The counter will be initialized by the FPGA automatically before generating the source files for Intel Quartus-Lite.
Binary Counter VHDL PCLK DE10-Lite circuit
Generating the source files for Intel Quartus-Lite.
First we will add the sources files, the VHDL and the QSF files. The VHDL file is the top-level entity wrapping the underlying components and connections around. The content of the QSF file will tell the software which FPGA pins are to be used for the logic inputs and outputs.
Next, we will compile the files for the FPGA.
As soon as the “Full Compilation was successful” message appears, we will program the device.
You will see the “Progress bar at 100%, successful” message and also you will see the counter lights come up counting up in binary.
If the output code reaches the maximum value of 15 the counter next state will be zero.
replacing the clock source with a push button
A counter can count not only a series of pulses but other events too. For example the number of times a push button has been pressed.
To demonstrate this, we will return to our original circuit and replace the the Clock Source with a Push Button. Let the push button PB generate a high level when it is pressed and a low level when it is at rest.
We will also place a Resistor and a Digital High Source. No, we can start the simulation by pressing the TR button. When the button is pressed a rising edge occurs on the clock input of binary counter entity and the counter outputs will produce the next binary code.
Binary Counter VHDL Btn circuit
implementing this circuit in a real fpga environment using the Terasic DE10-Lite board
First we will remove the Push button, the Resistor and the Pulse Source. Next, we will place 2 FPGA Pin Connectors named as KEY0 and KEY1.
The KEY0 button will be connected to the resetn input of the counter, while KEY1 will provide the clock. We will place four more Pin Connectors and connect them to the Logic Indicators QA, QB, QC, QD. Then we will set their parameters as we did previously: LEDR[0], LEDR[1], LEDR[2] and LEDR[3].
Since we will not need the Logic Indicators we can delete them now.
Binary Counter VHDL Btn DE10-Lite circuit
Every time the KEY1 is pressed and released a rising edge is applied to the counter clock input and as a result it counts up by one.
If we press KEY0 then the Counter outputs go to zero.
The counter is a widely used sequential logic where the output depends on the sequence of past inputs and a present value of the input signals. In the case of a counter the input signal is the clock and the output’s value represents a number. The counter circuit is usually built up with flip flops.
Now, in this video our counter will be based on the Verilog hardware description language.The textual description of the hardware greatly enhances portability and reusability.
In our first exemple, Binary Counter Verilog.tsc we will replace the flip-flops by a macro.
Binary Couner Verilog circuit
Let’s examine the Macro
The macro has two inputs, one for the Clock (clk) and another for the active-low reset (resetn). Clk is connected to the Clock source, and resetn is connected to the reset Pulse Source.
The four outputs (QA, AB, QC, QD) provide the counter value.
The Binary Counter module has the same inputs and outputs as the macro shape.
The always block is executed when the clock rising from low to high or the resetn input falling from high to low.
Instead of implementing a counter with flip flop inference, we increment the q register if the reset is held high and the Clk is rising. Therefore, the counter counts the Clk rising edges.
If the resetn is low then the q is reset to the value of zero.
The q register bit values are assigned to qa, qb, qc, qd respectively.
Each output line represents a binary digit.
The Clock source is one hertz for good interactivity. Following the practice, we assign a short clear pulse by PS at the very beginning before the counting sequence to reset the counter.
Let’s start the Transient analysis and examine the circuit operation
When the clock is changing low to high the indicator turns red then the qa, the least significant bit, toggles. Then, at each rising edge of the clock, the count value goes up by one.
When the counter reaches the maximum value (binary 1111), the output goes zero. Now before testing our circuit in a real FPGA environment we need to extend our schematic with FPGA pin connectors. We will use a Terasic DE10-Lite Intel FPGA board.
Extending the Schematic with FPGA Pin connectors.
Regarding the DE10-Lite board we should note that such a board has clock generators with 50 megahertz output frequency.
Since the board doesn’t provide a one hertz clock, we have to apply a Prescaler which will produce that from the DE10-Lite 50 MHertz oscillator.
The prescaler macro has one input named Clk and one output named PClk. The Clock frequency at Clk input is 100 megahertz and it is one hertz at the PClk output by default. To adjust the VHDL code to the board 50 megahertz frequency, double-click the Prescaler macro, then in the properties window click the three dots at the end of the HDL code field. Modify the ‘Presc < 50000000’ expression constant to 25 million, then save by pressing OK.
The prescaler itself is also a counter. When the counter reaches 25 million the PClk output is toggled, so that the frequency of the clock at this output is one hertz. This is an additional logic to reach slow human readable operation speed.
Inserting a prescaler
Binary Counter Verilog PClk DE10-Lite circuit
Now let’s insert this Prescaler as a macro which has been written in VHDL. In TINACloud, you can mix VHDL and Verilog.
Next double-click the pin connector then in the properties window click the three dots at the end of the Pin settings field. In the Device section click the Terasic DE10-Lite, then select CLOCK under the Group section and MAX10_CLK1_50 under the Pin section.
Click ok to accept the settings. Rename the label of pin one as Clk as well and click ok.
Now, insert the FPGA pin connectors for the four outputs of the circuit and assign them to the LEDs: LEDR[0] LEDR[1] LEDR[2] and LEDR[3]. Set the LED names to LEDR[0] LEDR[1] LEDR[2] and LEDR[3] respectively.
Finally remove the Pulse Source, then select a Digital High Source from the Sources Toolbar and connect it to the resetn input. Next, rename its laber as High.
A reset pulse will be assigned by the FPGA automatically.
Now, let’s generate the source files for Intel Quartus-Lite.
As soon as the “Quartus Prime Full Compilation was successful” message appears, right-click the Program Device, then click Open.
Click the Start button to program the device.
You will see the “Progress bar at 100%, successful” message and the counter lights come up counting up in binary.
If the output code reaches the maximum value of 15 the counter next state will be zero.
Slowing down the Prescaler and changing the Macro code
The simulation of this circuit must be handled with care because the prescaler has to count to a very large number, before the output toggles, we have to slow down this module therefore in the simulation.
Now, change the input clock frequency to 100 hertz, and change the macro code so that the counter counts up to 50 instead of 25 million. This way we will have a one hertz clock coming out of the prescaler for the simulator.
Replacing the Clock Source with a Push Button
Binary Counter Verilog Btn circuit
Binary Counter Verilog Btn circuit
Delete the Clock Source, then select a Push button from the Switches Toolbar.
The Push button (PB) will generate a high level when it is pressed and a low level when it is at rest. When the button is pressed a rising edge occurs on the clock input of binary counter module and the counter outputs will produce the next binary code.
Implementing this circuit on an FPGA
Here we note, that the mechanical switches and push buttons have contact bouncing problems. If we press a button once in the real world that may generate a series of pulses.
To debounce the buttons, either FPGA logic or external circuit is necessary.
The Terasic FPGA board will eliminate the unwanted glitches by a Schmitt trigger circuit constructing a single low pulse when the button is pressed.
Modifying the circuit for using these buttons
Binary Counter Verilog Btn DE10-Lite circuit
Binary Counter Verilog Btn DE10-Lite circuit
First, remove the push button and the resistor. These are not necessary because they are on the board and don’t belong to the synthesizable logic. Remove the pulse source and the Digital High Source as well. Now, select two FPGA pins then place them on the workspace.
The KEY0 button will be connected to the resetn input of the counter, while KEY1 will provide the clock.
For Pin2, select KEY[1], rename label to Clk.
Place four more Pin connectors and connect them to the Logic Indicators QA, QB, QC, QD. Set their parameters and rename them as we did previously.
Since we will not need the Logic Indicators we can delete them.
Now, the circuit is ready for the export of Intel Quartus.
Let’s generate the source files.
Now, connect DE10-Lite with the Quartus machine via USB.
Here every time the KEY1 is pressed and released a rising edge is applied to the counter clock input and as a result, it counts up by one.
If we press KEY0 then the counter outputs go to zero.
In this tutorial video our circuits are counters. The counter is a widely used sequential logic, where the output depends on the sequence of past inputs, and a present value of the input signals.
Binary up Counter circuit
Our first example is a binary up counter circuit.
The counter is constructed from 4, rising edge sensitive D flip-flops counting from 0 to 15. Flip-flops store the count until the next event, when the clock signal produces a low to high transition.
Binary up counter circuit
The least significant bit is QA. The clock source is 1Hz for good interactivity. Following the practice, we assign a short clear pulse by PS at the very beginning before the counting sequence to reset the flip-flops. The full name of the circuit is “asynchronous binary up counter”. Asynchronous, because each flip-flop has a distinctive clock, usually from the previous stage.
Press the Transient Interactive button. As we can see when the clock is changing low to high the indicator turns red, then the least significant flip-flop, U1, will toggle, and this effect propagates through each flip-flop.
This ripple phenomenon causes a delay in the nanosecond domain, but if we don’t care about an immediate result, short transients are acceptable.
Inserting a Prescaler
Before testing our circuit in a real FPGA environment, we need to extend our schematic with FPGA pin connectors.
Since the board doesn’t provide a 1Hz clock, we have to apply a Prescaler which will produce that from the DE10-Lite 50MHz oscillator.
The PreScaler macro has one input named “Clk” and one output named “PClk”. The clock frequency at Clk input is 100MHz, and it is 1Hz at the PClk output by default.
The Prescaler itself is also a counter. When the counter reaches 25,000,000, the PClk output is toggled so that the frequency of the clock at this output is 1Hz. This is an additional logic to reach slow, human readable operation speed.
The simulation of this circuit must be handled with care. Because the Prescaler has to count to a very large number before the output toggles, we have to slow down this module therefore in the simulation.
Using a Push button
Replace the Clock Source with a Push button.
Let the Push button (PB) generate a high level, when it is pressed and a low level when it is at rest. When the button is pressed, a rising edge occurs on the clock input of the first flip-flop, and the counter outputs will produce the next binary code.
If we press a button once in the real world that may generate a series of pulses. To debounce the buttons, either FPGA logic or external circuit is necessary.
The Terasic FPGA board will eliminate the unwanted glitches by a Schmitt trigger circuit constructing a single low pulse when the button is pressed.
User-defined Push-buttons (DE10-Lite User Manual)
Modifying the circuit for using these buttons
Remove the Push button and the Resistor. These are not necessary because they are on the board and don’t belong to the synthesizable logic. Remove the Pulse Source as well.
The KEY0 button will be connected to the Clear input of the flip-flops, while KEY1 will provide the Clock.
Since we will not need the Logic Indicators we can delete them.
The circuit is ready for the export of Intel Quartus.
Here every time the KEY1 is pressed and released a rising edge is applied to the counter clock input and as a result it counts up by one.
If we press KEY0 then the counter outputs go to zero.
Now, in this video tutorial our circuit, a full adder will be based on the Verilog hardware description language.
The textual description of the hardware greatly enhances portability and reusability. By using hardware description languages describing the fundamental operations, structures and connections, virtually any logical circuit can be defined.
As we stated earlier TINACloud works with schematics, but we can also place HDL macros, including VHDL and Verilog, in the design.
First, we will test our circuit with Verilog circuit simulation in TINACloud.
The circuit operates like a half adder while Carry_In value is low.
When both inputs are low while Carry_In is also low, then Sum and Carry_Out are also low.
When just one input is low while Carry_In is low, then Sum is high and Carry_Out is also low.
When both inputs are high when Carry_In is low, then Sum is low and Carry_Out is high.
Now, let’s see what happens when Carry_In is high.
When Carry_In is high while both inputs are low, then Sum is high too and Carry_Out is low.
When Carry_In is high while only one input is high, then Sum is low and Carry_Out is also high.
When Carry_In is high while both inputs are high, then Sum and Carry_Out are also high.
If Carry_in is high, then the output values change as if we had added one to the full adder.
Next, we will export the Verilog to the Intel Quartus software, compile it and load the resulting bitstream into the Terasic DE10-Lite Intel FPGA board.
Finally, we will present how our simulated full adder circuit works along with the programmed Terasic DE10-Lite hardware and show that in all cases, the results are exactly the same.
