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• Verilog Simulation
• Verilog-A & AMS Simulation
• VHDL Simulation
• VHDL-AMS Simulation
• SystemC Simulation

SystemVerilog is an extension of the Verilog hardware description language, also included in TINA.
In TINA SystemVerilog is automatically translated to SystemC which can be compiled with MS Visual Studio providing a very fast and optimized code. You can find several circuit examples in the Examples\HDL\SystemVerilog folder of TINA.

SystemVerilog example: